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Electrical Specifications Subject to Change
FEATURES

LTC2970/LTC2970-1 Dual I2C Power Supply Monitor and Margining Controller DESCRIPTIO
The LTC(R)2970 is a dual power supply monitor and margining controller with an SMBus compatible I2C bus interface. A low-drift, on-chip reference and 14-bit A/D converter allow precise measurements of supply voltages, load currents or internal die temperature. Fault management allows ALERT to be asserted for configurable over and under voltage fault conditions. Two voltage buffered, 8-bit IDACs allow highly accurate programming of DC/DC converter output voltages. The IDACs can be configured to automatically servo the power supplies to the desired voltages using the ADC. The LTC2970-1 adds a tracking feature that can be used to turn multiple power supplies on or off in a controlled manner. The bus address is set to 1 of 9 possible combinations by pin strapping the ASEL0 and ASEL1 pins. The LTC2970/ LTC2970-1 are packaged in the 24-lead, 4mm x 5mm QFN package.
, LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
Less Than 0.5% Total Unadjusted Error 14-Bit ADC with On-Chip Reference Dual, 8-Bit IDACs with 1x Voltage Buffers Linear, Voltage Servo Adjusts Supply Voltages by Ramping IDAC Outputs Up/Down I2CTM Bus Interface (SMBus Compatible) Extensive, User Configurable Fault Monitoring On-Chip Temperature Sensor Available in 24-Lead 4mm x 5mm QFN Package
APPLICATIO S

Dual Power Supply Voltage Servo Monitoring Supply Voltage and Current Programmable Power Supplies Programmable Reference
TYPICAL APPLICATIO
Dual Power Supply Monitor and Controller (One of Two Channels Shown)
8V TO 15V 0.1F 12VIN VIN IN OUT 1/2 LTC2970 GPIO_CFG I+ I- DC/DC CONVERTER VIN0_BM VIN0_BP VOUT0 VIN0_AP RUN/SS FB LOAD IOUT0 VIN0_AM ALERT SCL SDA I2C BUS SMBUS COMPATIBLE VDD ERROR (%) 0.1F 0.25
(
)
GPIO_0 REF 0.1F
GND
SGND
GND ASEL0 ASEL1
29701 TA01
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ADC Total Unadjusted Error vs Temperature
0.50 15 PARTS MOUNTED ON PCB
0
-0.25
-0.50 -50
ADC VIN = 5V -25 50 25 TEMPERATURE (C) 0 75 100
29701 TA01b
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LTC2970/LTC2970-1 ABSOLUTE
(Notes 1 and 2)
AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW GPIO_CFG ASEL0 ASEL1 RGND REF
Supply Voltages: VDD ......................................................... -0.3V to 6V 12VIN .................................................... -0.3V to 15V Digital Input/Output Voltages: ASEL0, ASEL1 ............................ -0.3V to VDD + 0.3V SDA, SCL, GPIO_CFG, ALERT, GPIO_0, GPIO_1.......................... -0.3V to 6V Analog Voltages: VIN0_AP, VIN0_AM, VIN0_BP, VIN0_BM, VIN1_AP, VIN1_AM, VIN1_BP, VIN1_BM, VOUT0, VOUT1 .............. -0.3V to 6V IOUT0, IOUT1, REF......................... -0.3V to VDD + 0.3V RGND.................................................... -0.3V to 0.3V Operating Temperature Range: LTC2970C ................................................ 0C to 70C LTC2970I ............................................. -40C to 85C Storage Temperature Range...................- 65C to 150C Lead Temperature (Soldering, 10 sec) .................. 300C
24 23 22 21 20 VIN0_AP 1 VIN0_AM 2 VIN0_BP 3 VIN0_BM 4 VIN1_AP 5 VIN1_AM 6 VIN1_BP 7 8 VIN1_BM 9 10 11 12 VOUT0 VOUT1 VDD 12VIN 25 19 SDA 18 SCL 17 ALERT 16 GPIO_0 15 GPIO_1 14 IOUT0 13 IOUT1
UFD PACKAGE 24-LEAD (4mm x 5mm) PLASTIC QFN
TJMAX = 125C, JA = 37C/W EXPOSED PAD (PIN 25) IS GND MUST BE SOLDERED TO PCB
ORDER PART NUMBER LTC2970CUFD LTC2970IUFD LTC2970CUFD-1 LTC2970IUFD-1
UFD PART MARKING* 2970 2970 29701 29701
Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. V12VIN = 12V, VDD and REF pins floating unless otherwise indicated, CVDD = 100nF and CREF = 100nF.
SYMBOL IV12 IDD VLKO VDD PARAMETER 12VIN Supply Current VDD Supply Current VDD Undervoltage Lockout VDD Undervoltage Lockout Hysteresis Supply Input Operating Range Regulator Output Voltage Regulator Output Voltage Temperature Coefficient Regulator Output Voltage Load Regulation Regulator Line Regulation V12VIN 12VIN Supply Operating Range -1mA IVDD 0 8V V12VIN 15V, IVDD = 0mA

ELECTRICAL CHARACTERISTICS
CONDITIONS V12VIN = 12V, VDD Floating VDD = 5V, V12VIN = VDD VDD Ramping-Down, V12VIN = VDD

MIN
TYP 4.24 3.7
MAX 7.5 5 4.4 5.75
UNITS mA mA V mV V V ppm/C ppm/mA ppm/V
Power-Supply Characteristics
3.7 4.5 4.75
4.14 118
8V V12VIN 15V, -1mA IVDD 0
4.95 10 160 80
5.25
Regulator Output Short-Circuit Current V12VIN = 12V, VDD = 0V
-5 8
-34
-63 15
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mA V
W
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WW
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LTC2970/LTC2970-1 ELECTRICAL CHARACTERISTICS
SYMBOL VREF PARAMETER Reference Output Voltage Reference Voltage Temperature Coefficient Reference Overdrive Voltage Input Range ADC Characteristics N_ADC TUE_ADC INL_ADC DNL_ADC VIN_ADC VOS_ADC GAIN_ADC TCONV_ADC CIN_ADC FIN_ADC ILEAK_ADC N_IOUT INL_IOUT DNL_IOUT IFS-IOUT IDRIFT-IOUT IOS-IOUT INL_VOUT DNL_VOUT VOS-VOUT VOUT Resolution Total Unadjusted Error Integral Nonlinearity Differential Nonlinearity Input Voltage Range Offset Error Offset Error Drift Gain Error Gain Error Drift Conversion Time Input Sampling Capacitance Input Sampling Frequency Input Leakage Current Resolution (Guaranteed Monotonic) Integral Nonlinearity Differential Nonlinearity Full-Scale Output Current Output Current Drift Offset Current Integral Nonlinearity Differential Nonlinearity Offset Voltage Output Voltage Drift Load Regulation Leakage Current Short-Circuit Current Low Short-Circuit Current High VIOUTn < VDD - 1.5V VIOUTn < VDD - 1.5V VIOUTn < VDD - 1.5V, DAC Code = 'hff DAC Code = 'hff DAC Code = 'h00 RIOUTn = 10k, No Load on VOUTn (Note 5) RIOUTn = 10k, No Load on VOUTn (Note 5) VOS = VOUTn - VIOUTn, No Load on VOUTn No Load on VOUTn 0.1V < VOUTn < VDD - 1.5V, IVOUTn Source = 1mA 0.1V < VOUTn < VDD - 1.5V, IVOUTn Sink = 1mA VOUTn High-Z, 0V VOUTn VDD VOUTn Shorted to GND VOUTn Shorted to VDD

The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. V12VIN = 12V, VDD and REF pins floating unless otherwise indicated, CVDD = 100nF and CREF = 100nF.
CONDITIONS MIN TYP 1.229 2 1 1.5 MAX UNITS V ppm/C V
Voltage Reference Characteristics
N_ADC = 8.192V/16384 VIN = 3V, VIN = VINn_xP - VINn_xM (Note 3) (Note 4) (Note 7)

500 0.5 -1 0 -1000 -316 0.19 2 4.5 0.5 6 1000 0.4 3 33.3 3 61.4
V/LSB % LSB LSB V V V/C % ppm/C ms pF kHz 0.1 A Bits 1 1 LSB LSB A ppm/C 0.1 0.5 0.5 A LSB LSB mV V/C ppm/mA ppm/mA 100 -50 50 nA mA mA
Full-Scale VIN = 6V
0V < VIN < 6V
IDAC Output Current Characteristics 8
-236
-255 32
-276
Voltage Buffered IDAC Output Characteristics
1.6 0.17 -57 100 1
10
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LTC2970/LTC2970-1
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. V12VIN = 12V, VDD and REF pins floating unless otherwise indicated, CVDD = 100nF and CREF = 100nF.
SYMBOL VOS TMP GAIN_12VIN VIH VIL VHYST ILEAK CIN VIH_ASEL VIL_ASEL IIN,HL IIN,Z VOL IOH PARAMETER Offset Voltage Gain Gain Input High Threshold Voltage Input Low Threshold Voltage Input Hysteresis Input Leakage Current Input Capacitance Input High Threshold Voltage Input Low Threshold Voltage High, Low Input Current High Z Input Current Output Low Voltage Input Leakage Current ISINK = 3mA 0V VIN 6V ASEL[1:0] = 0, VDD

ELECTRICAL CHARACTERISTICS
CONDITIONS
MIN
TYP 3 0.25
MAX
UNITS mV C/LSB
Soft Connect Comparator Characteristics (CMP0, CMP1) Temperature Sensor Characteristics 12VIN Voltage Divider Characteristics 0.329 0.333 0.335 2.1 1.6 1.5 1.0 0.08 0V VIN 6V 1 10 VDD - 0.5 0.5 20 2 0.4 1 V/V V V V V V A pF V V A A V A Digital Inputs SCL, SDA, GPIO_CFG, GPIO_0, GPIO_1 SDA, SCL GPIO_CFG, GPIO_0, GIPO_1 SDA, SCL GPIO_CFG, GPIO_0, GIPO_1
Three State Inputs ASEL[1:0]
Open Drain Outputs SDA, GPIO_CFG, GPIO_0, GPIO_1, ALERT
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C.
SYMBOL fSCL tLOW tHIGH tBUF tHD,STA tSU,STA tSU,STO tHD,DAT tSU,DAT tSP PARAMETER Serial Clock Frequency Serial Clock Low Period Serial Clock High Period Bus Free Time Between Stop and Start Start Condition Hold Time Start Condition Setup Time Stop Condition Setup Time CONDITIONS (Note 6) (Note 6) (Note 6) (Note 6) (Note 6) (Note 6) (Note 6)

MIN 10 1.3 0.6 1.3 600 600 600 0 300 100
TYP
MAX 400
UNITS kHz s s s ns ns ns ns ns ns ns
I2C Interface Timing Characteristics
Data Hold Time (LTC2970 Receiving Data) (Note 6) Data Hold Time (LTC2970 Transmitting Data) Data Setup Time (LTC2970 Receiving Data) Pulse Width of Spike Suppressed (Note 6) (Note 6)
900 98
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LTC2970/LTC2970-1 ELECTRICAL CHARACTERISTICS
SYMBOL tSETUP_GPIO PARAMETER GPIO_0 and GPIO_1 Setup Time
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C.
CONDITIONS GPIO_0 and GPIO_1 input setup time prior to the 26th rising SCL of an IO() I2C read. These inputs must be valid and stable by this time to be returned in the IO() read result. (Note 6) GPIO_0 and GPIO_1 input hold time after the 26th rising SCL of an IO() I2C read. These inputs must be held until this amount of time has elapsed to be returned in the IO() read result. (Note 6) GPIO_0 and GPIO_1 output delay after the 35th rising SCL of an I2C write. These outputs will become high impedance or begin driving low by this time. (Note 6) The LTC2970 will release the I2C bus and terminate the current command if the command is not completed before this amount of time has elapsed. After selecting a new ADC channel, the LTC2970 will wait this amount of time to allow the analog input to settle before beginning an ADC conversion. LTC2970-1 Only: The LTC2970-1 will abort a pending SYNC() command if a tracking command is not received before this amount of time has elapsed. LTC2970-1 Only: After the tracking algorithm asserts CPIO_CFG low, the LTC2970-1 will delay disconnecting the IDACs from the power supply feedback nodes by this amount of time. Used while tracking power supplies on. LTC2970-1 Only: After the tracking algorithm asserts CPIO_CFG high, the LTC2970-1 will wait this amount of time before starting to decrement Chn_a_ delay_track[9:0]. Used while tracking power supplies off. LTC2970-1 Only: The LTC2970-1 changes Chn_a_delay_track[9:0] at this rate.
MIN 2.5
TYP
MAX
UNITS s
tHOLD_GPIO
GPIO_0 and GPIO_1 Hold Time
2.5
s
tOUT_GPIO
GPIO_0 and GPIO_1 Output Time
2.5
s
Internal Timers tTIMEOUT_SMB Stuck BUS Timer 24 32 39 ms
tSETUP_ADC
ADC Channel Setup Time
304
s
tTIMEOUT_
SYNC
Tracking SYNC Failure Timer
255
ms
tHOLD_TRACK
Tracking IDAC Disconnect Delay
32
ms
tSETUP_TRACK Tracking IDAC Disconnect Delay
32
ms
tDEC_TRACK
Tracking IDAC Decrement Rate
88
s/LSB
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified. VIN Note 3: TUE (%) is defined as % Gain Error + (INL * 500V/LSB + V ) * 100 OS Note 4: Integral nonlinearity (INL) is defined as the deviation of a code from a straight line passing through the actual endpoints (0V and 6V)
of the transfer curve. The deviation is measured from the center of the quantization band. Note 5: Nonlinearity is defined from the first code that is greater than or equal to the maximum offset specification to code 255 (full-scale). Note 6: Maximum capacitive load, CB, for SCL and SDA is 400pF. Data and clock risetime (tr) and falltime (tf) are: (20 + 0.1 * CB)(ns) < tr < 300ns and (20 + 0.1 * CB)(ns) < tf < 300ns. CB = capacitance of one bus line in pF. SCL and SDA external pull-up voltage, VIO, is 3V < VIO < 5.5V. Note 7: This specification is guaranteed by design.
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LTC2970/LTC2970-1 TI I G DIAGRA W
The I2C Bus Specification
tr tSU;DAT tf tHD;STA tSP tr tBUF tHD;DAT tHIGH tSU;STA REPEATED START CONDITION tSU;STO STOP START CONDITION CONDITION
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SDA tf SCL tHD;STA START CONDITION tLOW
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LTC2970/LTC2970-1 TYPICAL PERFOR A CE CHARACTERISTICS
ADC Total Unadjusted Error vs Temperature
0.050 BASED ON AVERAGE OF 15 PARTS 0.025 ASSEMBLED ON 1/8" THICK PCB 1V 0 ERROR (LSBs) 2.5 2.0 1.5 ERROR (LSBs) 1.8V 2.5V 3.3V ADC VIN = 5V 1.0 0.5 0 -0.5 -1.0 -25 0 25 50 TEMPERATURE (C) 75 100 0 1 4 3 2 INPUT VOLTAGE (V) 5 6
29701 G02
-0.025 ERROR (%) -0.050 -0.075 -0.100 -0.125 -0.150 -0.175 -50
ADC Zero Code Center Offset Voltage vs Temperature
-305 -310 REJECTION (dB) -315 VOS (V) -320 -325 -330 -335 -50 0 -10 -20
-40 -50 -60 -70 -80 -90
REJECTION (dB)
-25
0 25 50 TEMPERATURE (C)
ADC Noise Histogram
10,000,000 1,000,000 NUMBER OF READINGS 100000 10,000 1000 100 10 1 -2 1 OUTPUT CODE (LSBs) -1 0 2
29701 G07
VIN = 0V
ERROR (LSBs)
ERROR (LSBs)
UW
29701 G01
ADC INL
1.00 0.75 0.50 0.25 0 -0.25 -0.50 -0.75 -1.00
ADC DNL
0
1
2 4 3 INPUT VOLTAGE (V)
5
6
29701 G03
ADC Rejection vs Frequency at VIN
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 1 100 10 1000 FREQUENCY AT VIN (Hz) 10000
29701 G05
ADC Rejection vs Frequency at VIN
-30
-100 75 100
0
5000 10000 15000 20000 25000 30000 FREQUENCY AT VIN (Hz)
29701 G06
29701 G04
Voltage Buffered IDAC INL
0.50 CHANNELS 0 AND 1 SHOWN RIOUT0 = RIOUT1 = 10k 0.50
Voltage Buffered IDAC DNL
CHANNELS 0 AND 1 SHOWN RIOUT0 = RIOUT1 = 10k
0.25
0.25
0
0
-0.25
-0.25
-0.50
-0.50 0 50 150 100 DAC CODE 200 250
29701 G08
0
50
150 100 DAC CODE
200
250
29701 G09
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LTC2970/LTC2970-1 TYPICAL PERFOR A CE CHARACTERISTICS
IDAC Output Current vs Temperature
257.4 257.2 OUTPUT CURRENT (A) OFFSET VOLTAGE (mV) 257.0 256.8 256.6 256.4 256.2 -50 IDAC CODE = 'hff RIOUT = 13k 1.620 1.615 1.610 1.605 1.600 1.595 1.590 -50 OUTPUT VOLTAGE (V)
-25
0 25 50 TEMPERATURE (C)
Voltage Buffered IDAC Load Regulation Sinking
0.35 0.30 25C OUTPUT VOLTAGE (V) 10mV PER DIVISION 0.25 0.20 -45C 0.15 0.10 0.05 0 0 2 4 6 8 10 CURRENT (mA)
29701 G13
VIOUT = 0.1V
CODE 'h80
10mV PER DIVISION
Voltage Buffered IDAC Transient Response During Transition from On State to High-Z State
100k SERIES RESISTANCE ON VOUT RIOUT = 10k 1.5 1.0 10mV PER DIVISION HIGH-Z 0.5 ERROR (C) 0 -0.5 -1.0
VDD (V)
CONNECTED
10s PER DIVISION
29701 G16
8
UW
75 90C
VOUTn Offset Voltage vs Temperature
IDAC CODE = 'h00 3.500
Voltage Buffered IDAC Load Regulation Sourcing
25C 3.498 -45C 3.496
3.494 90C 3.492 VIOUT = 3.5V 0 -2 -6 -4 CURRENT (mA) -8 -10
29701 G12
100
3.490 -25 0 25 50 TEMPERATURE (C) 75 100
29701 G11
Voltage Buffered IDAC Transient Response to 1LSB DAC Code Change
100k SERIES RESISTANCE ON VOUT RIOUT = 10k
Voltage Buffered IDAC SoftConnect Transient Response
100k SERIES RESISTANCE ON VOUT RIOUT = 10k CODE 'h80 HIGH-Z
CODE 'h7f
CONNECTED
1s PER DIVISION
29701 G14
5s PER DIVISION
29701 G15
Temperature Sensor Error vs Temperature
4.945 4.944 4.943 4.942 4.941 4.940 4.939
VDD Regulator Output Voltage vs Temperature
V12VIN = 12V IVDD = 0A
-1.5 -50
-25
0 25 50 TEMPERATURE (C)
75
100
4.938 -50
-25
50 25 0 TEMPERATURE (C)
75
100
29701 G18
29701 G17
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LTC2970/LTC2970-1 TYPICAL PERFOR A CE CHARACTERISTICS
VDD Regulator Load Regulation
0 -100 -200 VDD (ppm) VDD (ppm) -300 -45C -400 -500 -600 25C -700 -800 V12VIN = 12V 0 -1 -3 CURRENT (mA) -2 -4 -5
29701 G19
200 100 0 -100 -200 90C -300 -400 -500 8 9 10 10 12 V12VIN (V) 13 14 15 25C 90C -45C
SHORT-CIRCUIT CURRENT (mA)
PI FU CTIO S
VIN0_AP (Pin 1): Positive CH0_A ADC Multiplexer Input. The output of the differential, 7:1 multiplexer connects to the input of the ADC. CH0_A can be configured to servo IDAC0. VIN0_AM (Pin 2): Negative CH0_A ADC Multiplexer Input. The output of the differential, 7:1 multiplexer connects to the input of the ADC. CH0_A can be configured to servo IDAC0. VIN0_BP (Pin 3): Positive CH0_B ADC Multiplexer Input. The output of the differential, 7:1 multiplexer connects to the input of the ADC. CH0_B is a voltage monitor input only. VIN0_BM (Pin 4): Negative CH0_B ADC Multiplexer Input. The output of the differential, 7:1 multiplexer connects to the input of the ADC. CH0_B is a voltage monitor input only. VIN1_AP (Pin 5): Positive CH1_A ADC Multiplexer Input. The output of the differential, 7:1 multiplexer connects to the input of the ADC. CH1_A can be configured to servo IDAC1. VIN1_AM (Pin 6): Negative CH1_A ADC Multiplexer Input. The output of the differential, 7:1 multiplexer connects to the input of the ADC. CH1_A can be configured to servo IDAC1. VIN1_BP (Pin 7): Positive CH1_B ADC Multiplexer Input. The output of the differential, 7:1 multiplexer connects to the input of the ADC. CH1_B is a voltage monitor input only. VIN1_BM (Pin 8): Negative CH1_B ADC Multiplexer Input. The output of the differential, 7:1 multiplexer connects to the input of the ADC. CH1_B is a voltage monitor input only. VDD (Pin 9): VDD Power Supply, Voltage Monitor Input, and Internal 5V Regulator Output. The supply input range is 4.5V to 5.75V. The VDD pin voltage can be connected to the ADC through an internal mux. Bypass the VDD pin to device ground with a 100nF capacitor (CVDD). If no 5V input voltage supply is available, float the VDD pin and power the LTC2970 from the 12VIN pin. 12VIN (Pin 10): 12V Power Supply and Voltage Monitor Input. An internal regulator generates 5V from 12VIN. The input range for 12VIN is 8V to 15V. Bypass this pin with a 100nF capacitor. The regulator's output is connected to the VDD pin. The 12VIN pin voltage can also be monitored by the ADC through a 3:1 attenuator and the internal mux. If no 12V supply input is available, tie the 12VIN to the VDD pin and operate from 4.5V to 5.75V. VOUT0 (Pin 11): CH0 Voltage Output. Buffered version of IDAC0 output voltage.
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VDD Regulator Line Regulation
400 300 NO LOAD ON VDD -25
VDD Regulator Short-Circuit Current vs Temperature
V12VIN = 12V VDD = 0V
-30
-35
-40 -50
-25
0 25 50 TEMPERATURE (C)
75
100
29701 G21
29701 G20
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LTC2970/LTC2970-1 PI FU CTIO S
VOUT1 (Pin 12): CH1 Voltage Output. Buffered version of IDAC1 output voltage. IOUT1 (Pin 13): IDAC1 Current Output. Connect a resistor between this pin and the point-of-load ground for channel 1. The IDAC sources between 0 and 255A. IOUT0 (Pin 14): IDAC0 Current Output. Connect a resistor between this pin and the point-of-load ground for channel 0. The IDAC sources between 0 and 255A. GPIO_1 (Pin 15): General Purpose Input or Open Drain Digital Output. GPIO_1 can be configured as the IDAC Fault or Faults output, a digital input, or an open-drain digital output. GPIO_0 (Pin 16): General Purpose Input or Open Drain Digital Output. GPIO_0 can be configured as the voltage monitor power-good or power-good bar output, a digital input, or a programmable open-drain output. Power good is the NOR of all instantaneous OV and UV faults; it does not include IDAC faults. ALERT (Pin 17): Open Drain Digital Output. Connect the SMBALERT signal to this pin. ALERT is asserted low when either IDAC0 or IDAC1 rails out (optional), or when one of the monitored voltages ventures outside its UV and OV OPERATIO thresholds (also optional). SCL (Pin 18): Serial Bus Clock Input. SDA (Pin 19): Serial Bus Data Input and Output. GPIO_CFG (Pin 20): GPIO Configuration Digital Input and Open Drain Output. Pulling GPIO_CFG high will cause the GPIO_0 and GPIO_1 open-drain outputs to automatically assert low after a power-on reset. If GPIO_CFG is pulled low, then GPIO_0 and GPIO_1 do not assert low after power-up. ASEL1 (Pin 21): Slave Address Select Bit 1. Tie this pin to the VDD pin, ground, or float in order to select the address location (see Table 2). ASEL0 (Pin 22): Slave Address Select Bit 0. Tie this pin to the VDD pin, ground, or float in order to select the address location (see Table 2). REF (Pin 23): Internal Reference Output or ADC Reference Overdrive Input. The voltage at this pin determines the full-scale input voltage of the delta-sigma ADC (VFULLSCALE = 6.65 * VREF , typically). An internal 3.5k resistor decouples the reference output from this pin. Bypass this pin to RGND with a 100nF capacitor (CREF). RGND (Pin 24): Reference Ground. Connect to device ground. GND (Pin 25): Device Ground. Must be soldered to ground.
10
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LTC2970/LTC2970-1 BLOCK DIAGRA
12VIN 10 2R R VDD VDD 9 12VP 12VM VDDP GND 25 VDDM VDD
TEMP SENSOR
TSNSP TSNSM
VIN0_AP VIN0_AM VIN0_BP VIN0_BM VIN1_AP VIN1_AM VIN1_BP VIN1_BM
1 2 3 4 5 6 7 8
CH0_AP 0A TO 255A CH0_AM CH0_BP CH0_BM CH1_AP CH1_AM CH1_BP CH1_BM 7:1 MUX 6.65X (TYP) 3.5k ADC CLOCKS VDD IDAC1 8 BITS 14-BIT DELTA-SIGMA A/D 13 IOUT1
REF 23 RGND 24
SCL 18 SDA 19 ASEL0 22 ASEL1 21 I2C BUS INTERFACE (400kHz, SMBUS COMPATIBLE) CLOCK GENERATION
GPIO_0 16 GPIO_1 15 ALERT 17 GPIO_CFG 20
SERVO CONTROLLER DAC SOFT CONNECT FUNCTION SERVO FUNCTION MONITOR FUNCTION MANAGE FAULT REPORTING WATCH DOG TRACKING CONTROL (LT2970-1)
W
5V REGULATOR VIN VOUT IDAC0 8 BITS 0A TO 255A 14 IOUT0
+
CMP0
+
VBUF0
-
11 VOUT0
-
POR UVLO
+ -
+
CMP1
+
VBUF1
-
12 VOUT1
-
REFERENCE 1.229V (TYP)
20
RAM ADC_Results MONITOR LIMITS SERVO TARGETS
18
POR
OSCILLATOR
7 2 POR
REGISTERS I/O CONFIGURATION IDAC0 IDAC1 ADC MONITOR FAULT ENABLE INSTANTANEOUS FAULTS LATCHED FAULTS
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LTC2970/LTC2970-1 TABLE OF CO TE TS
1. LTC2970 Operation Overview .............................................................................................................................14 2. I2C Serial Digital Interface .................................................................................................................................15 3. Register Command Set.......................................................................................................................................16 4. Detailed I2C Command Register Descriptions ...................................................................................................17 5. Soft Connecting the LTC2970 to the Power Supply Feedback Node ..................................................................21 6. Hard Connecting the LTC2970 to the Power Supply Trim Pin ............................................................................21 7. Programming a Previously Connected IDAC ......................................................................................................22 8. Disconnecting the LTC2970 from the Power Supply Trim Pin ...........................................................................22 9. Tracking Power Supplies Overview (LTC2970-1 Only).......................................................................................22 10. Tracking Power Supplies On (LTC2970-1 Only) .................................................................................................22 11. Tracking Power Supplies Off (LTC2970-1 Only) .................................................................................................23 12. Continuous Power Supply Voltage Servo ...........................................................................................................24 13. One Time Power Supply Voltage Servo .............................................................................................................25 14. One Time Power Supply Voltage Servo with Repeat On Fault ..........................................................................25 15. Configuring ADC to Monitor Input Channels and Internal Temperature Sensor ................................................25 16. Generating and Monitoring Instantaneous Faults..............................................................................................26 17. Generating and Monitoring Latched Faults........................................................................................................27 18. General Purpose Input/Output Pins ....................................................................................................................28 19. Advanced Development Features .......................................................................................................................28
12
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(For Operations Sections)
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LTC2970/LTC2970-1 OPERATIO
1. LTC2970 Operation Overview The LTC2970 is designed to control and monitor two power supplies. The LTC2970's superior accuracy allows it to precisely servo each supply's output voltage over a wide range of operating conditions; increasing accuracy, reducing power requirements and component costs. Margining may be performed with equal ease and precision. The monitoring functions allow for increased reliability by alerting a system host about incipient failures before they occur. The seven channel ADC may also be used to monitor current, temperature, and the 5V or optional 12V supply. The LTC2970's unique architecture and control algorithm have been especially tailored for power supply management. The soft connect feature allows the LTC2970 to begin controlling a power supply without perturbing its initial value. The delta-sigma ADC architecture was specifically chosen to average out power-supply noise and allow the LTC2970 to ignore fast transients. Unlike discrete time DACs, the LTC2970's continuous time, voltage buffered IDAC is ideal for noise sensitive applications. The servo algorithm limits the IDAC step size to one LSB per iteration in order to minimize power supply transients. The point of load ground reference for the IDAC outputs minimize errors that would otherwise occur in a power system that experiences ground bounce. By selecting two resistor values, the user can choose the appropriate resolution while providing an important hardware range limit beyond which the supply may not be driven. The servo on fault option allows the LTC2970 to further reduce output voltage disturbances by only stepping the IDAC when the output voltage drifts outside of a user programmable window. The LTC2970 powers up in a high impedance state and will not interfere with default power supply operation. Similarly, powering down the LTC2970 will restore its high impedance state.
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All communication with the LTC2970 is performed over an industry standard I2C bus. The LTC2970 I2C interface also meets all SMBus setup times, hold times, and timeout requirements. The ALERT pin may be used to signal that one or more of the fourteen configurable fault limits have been reached. Each fault may be individually masked. The I2C interface supports word reads, word writes and the SMBus Alert Response Address protocol. Two general purpose IO pins may be used to provide additional fault information or user defined system control. Powering down the LTC2970 will not interfere with I2C operation. The LTC2970-1 enables power supply tracking and sequencing with the addition of a few external components. A special global address and synchronization command allow multiple LTC2970-1's to track and sequence multiple pairs of power supplies. The LTC2970 can perform the following operations: * Accept all programming commands and report status over the I2C or SMBus bus. * Command each voltage buffered IDAC to connect to the corresponding power supply's feedback node through an external resistor using the IDAC code that most closely approximates the feedback node's regulation voltage (Soft Connect). * Command each voltage buffered IDAC output to connect to the corresponding power supply's feedback node through an external resistor with a user-selected IDAC code (Hard Connect). * Change the code of a previously connected IDAC. * Disconnect each voltage buffered IDAC output from the power supply's feedback node. * LTC2970-1 Only: Track two power supplies up or down. Multiple LTC2970-1's can be configured to track simultaneously or in a sequence.
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LTC2970/LTC2970-1 OPERATIO
* Continuously servo one or both supplies to a programmed voltage. * Perform a one-time servo of one or both supplies to a programmed voltage and hold the servo codes in the controlling IDAC. * Perform a one time servo of one or both supplies to a programmed voltage and hold the code(s) in the controlling IDAC(s) until over/under voltage monitoring detects a fault, at which point a control bit may be used to allow the LTC2970 to servo back to the initial voltage target. * Select any combination of seven possible ADC channels to be monitored by the ADC. * Generate instantaneous faults based on user programmable over-voltage and under-voltage limits and fixed IDAC limits. The status of OR'd voltage limit faults and IDAC faults may be output over GPIO_0 and GPIO_1, respectively. * Enable instantaneous faults to set associated latched faults using the FAULT_EN register. The status of OR'd latched faults may be signalled using ALERT. * Configure the GPIO_0 and GPIO_1 pins to act as inputs or outputs. 2. I2C Serial Digital Interface
The LTC2970 communicates with a host (master) using the 2-wire, I2C serial bus interface. The Timing Diagram shows the timing relationship of the signals on the bus.
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The two bus lines, SDA and SCL, must be high when the bus is not in use. External pull-up resistors or current sources are required on these lines. The LTC2970 I2C interface is SMBus compatible; it meets all SMBus setup times, hold times and timeout requirements. The LTC2970 is a receive-only (slave) device. The LTC2970 can signal the host through the SMBALERT protocol that it wants to talk by asserting ALERT low. The LTC2970 supports the three I2C protocols summarized in Table 1. Slave Address The LTC2970 can respond to one of nine 7-bit addresses. The two slave address select pins (ASEL1 and ASEL0) are programmed by the user and determine the slave address, as shown in Table 2. The LTC2970 also supports the ARA address and a global address that allows multiple LTC2970s to be programmed with the same data simultaneously, as shown in Table 3.
Table 1. Supported I2C Command Types
READ DATA WORD: S:ADR:W:A:CMD:A:Sr:ADR:R:A:DATA:A:DATA:NACK:P WRITE DATA WORD: S:ADR:W:A:CMD:A:W:A:DATA:A:DATA:A:P ALERT RESPONSE S:ARA:R:A:ADR:NACK:P:
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LTC2970/LTC2970-1 OPERATIO
ADDRESS[7:0] (R/W = 0) 8'hB8 8'hBA 8'hBC 8'hBE 8'hD6 8'hD8 8'hDA 8'hDC 8'hDE
Table 2. LTC2970 Address Table
ADDRESS[7:1] 7'h5C 7'h5D 7'h5E 7'h5F 7'h6B 7'h6C 7'h6D 7'h6E 7'h6F ASEL1 L L L F F F H H H ASEL0 L F H L F H L F H
L: VASELn < VIL_ASEL F: ASELn Floating H: VASELn > VIH_ASEL
3. Registered Command Set
COMMAND FUNCTION FAULT() FAULT_EN() FAULT_LA_INDEX() FAULT_LA() IO() ADC_MON() *SYNC() VDD_ADC() VDD_OV() VDD_UV() V12_ADC() V12_OV() V12_UV() CH0_A_ADC() CH0_A_OV() CH0_A_UV() CH0_A_SERVO() CH0_A_IDAC() *CH0_A_IDAC_TRACK() *CH0_A_DELAY_TRACK() CH0_B_ADC() CH0_B_OV() CH0_B_UV() CH1_A_ADC() CH1_A_OV() CH1_A_UV() DESCRIPTION Instantaneous Fault Status For All Channels Enable For All Latched Faults and Servo On Fault Index to All Latched Faults Latched Fault Status For All Channels IO Control and Status Register Control Register For Selecting ADC Channels to Monitor Control Register For Synchronizing Tracking Across Multiple Devices VDDIN ADC Conversion Result Register VDDIN Over-Voltage Monitor Control Register VDDIN Under-Voltage Monitor Control Register 12VIN ADC Conversion Result Register 12VIN Over-Voltage Monitor Control Register 12VIN Under-Voltage Monitor Control Register CH0_A ADC Conversion Result Register CH0_A Over-Voltage Monitor Control Register CH0_A Under-Voltage Monitor Control Register CH0_A Voltage Servo Control Register CH0_A IDAC Control Register CH0_A IDAC Track Final Value Register CH0_A IDAC Track Delay Register CH0_B ADC Conversion Result Register CH0_B Over-Voltage Monitor Control Register CH0_B Under-Voltage Monitor Control Register CH1_A ADC Conversion Result Register CH1_A Over-Voltage Monitor Control Register CH1_A Under-Voltage Monitor Control Register R/W Read Only Read/Write Read Only Read Only Read/Write Read/Write Read/Write Read Only Read/Write Read/Write Read Only Read/Write Read/Write Read Only Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read Only Read/Write Read/Write Read Only Read/Write Read/Write DATA LENGTH 16 Bits 16 Bits 16 Bits 16 Bits 16 Bits 16 Bits 16 Bits 16 Bits 16 Bits 16 Bits 16 Bits 16 Bits 16 Bits 16 Bits 16 Bits 16 Bits 16 Bits 16 Bits 16 Bits 16 Bits 16 Bits 16 Bits 16 Bits 16 Bits 16 Bits 16 Bits COMMAND BYTE VALUE `h00 `h08 `h10 `h11 `h17 `h18 `h1F `h28 `h29 `h2A `h38 `h39 `h3A `h40 `h41 `h42 `h43 `h44 `h45 `h46 `h48 `h49 `h4A `h50 `h51 `h52
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Table 3. Special LTC2970 Addresses
ADDRESS[7:0] ADDRESS[7:1] FUNCTION (R/W = 0) ARA 8'h18 7'h0C This is the standard Alert Response Address for all SMBus devices. This address is independent of the value of the ASEL1 and ASEL0 pins. This a global address to which all LTC2970s will respond. This address is independent of the value of the ASEL1 and ASEL0 pins. Global 8'hB6 7'h5B
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LTC2970/LTC2970-1 OPERATIO
COMMAND FUNCTION CH1_A_SERVO() CH1_A_IDAC() *CH1_A_IDAC_TRACK() *CH1_A_DELAY_TRACK() CH1_B_ADC() CH1_B_OV() CH1_B_UV() TEMP_ADC() RESERVED()
3. Registered Command Set (Cont.)
DESCRIPTION CH1_A Voltage Servo Control Register CH1_A IDAC Control Register CH1_A IDAC Track Control Register CH1_A IDAC Track Delay Register CH1_B ADC Conversion Result Register CH1_B Over-Voltage Monitor Control Register CH1_B Under-Voltage Monitor Control Register Temperature ADC Conversion Result Register All other commands are reserved for future expansion and should not be written or read. R/W Read/Write Read/Write Read/Write Read/Write Read Only Read/Write Read/Write Read/Write Read/Write DATA LENGTH 16 Bits 16 Bits 16 Bits 16 Bits 16 Bits 16 Bits 16 Bits 16 Bits 16 Bits COMMAND BYTE VALUE `h53 `h54 `h55 `h56 `h58 `h59 `h5A `h68 `hXX
*LTC2970-1 Only. LTC2970 will not acknowledge these commands.
4. Detailed I2C Command Register Descriptions
FAULT: Instantaneous Fault Register - Read
BIT(s) b[0] b[1] b[2] b[3] b[4] b[5] b[6] b[7] b[8] b[9] b[10] b[11] b[12] b[13] SYMBOL Fault_ch0_a_ov Fault_ch0_a_uv Fault_ch0_a_idac Fault_ch0_b_ov Fault_ch0_b_uv Fault_ch1_a_ov Fault_ch1_a_uv Fault_ch1_a_idac Fault_ch1_b_ov Fault_ch1_b_uv Fault_vdd_ov Fault_vdd_uv Fault_v12_ov Fault_v12_uv Always Returns 0 OPERATION 0 = The associated channel is clear of instantaneous faults. 1 = The associated channel has an instantaneous fault. The reported faults are instantaneous and not latched. When used in conjunction with latched faults they may indicate faults that are transient in nature.
b[15:14] Reserved
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FAULT_EN: Fault Enabling Register - Read/Write
BIT(s) b[0] b[1] b[2] b[3] b[4] b[5] b[6] b[7] b[8] b[9] b[10] b[11] b[12] b[13] b[14] SYMBOL Fault_en_ch0_a_ov Fault_en_ch0_a_uv Fault_en_ch0_a_idac Fault_en_ch0_b_ov Fault_en_ch0_b_uv Fault_en_ch1_a_ov Fault_en_ch1_a_uv Fault_en_ch1_a_idac Fault_en_ch1_b_ov Fault_en_ch1_b_uv Fault_en_vdd_ov Fault_en_vdd_uv Fault_en_v12_ov Fault_en_v12_uv Fault_en_ch0_a_servo 0 = Do not re-servo CH0_A in response to instantaneous OV or UV fault. 1 = Repeat a one time servo of CH0_A in response to instantaneous OV or UV fault. CH0_A must have servo operation enabled with Ch0_a_idac_ servo_repeat set low, and Adc_mon_ ch0_a set high. 0 = Do not re-servo CH1_A in response to instantaneous OV or UV fault. 1 = Repeat a one time servo of CH1_A in response to instantaneous OV or UV fault. CH1_A must have servo operation enabled with Idac_ch1_a_ servo_repeat set low, and Adc_mon_ ch1_a set high.
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OPERATION 0 = The associated bit in the FAULT_LA register will always be 0. (default) 1 = Instantaneous faults reported in the FAULT register will set associated bit in the FAULT_LA register.
b[15]
Fault_en_ch1_a_servo
LTC2970/LTC2970-1 OPERATIO
4. Detailed I2C Command Register Descriptions (Cont.)
FAULT_INDEX: Latched Fault Index Register - Read
BIT(s) b[0] SYMBOL Fault_la_index OPERATION 0 = All faults indicated by FAULT_LA are clear. 1 = One or more faults indicated by FAULT_LA are set. This register allows a summary of all latched faults to be viewed in a single read without resetting latched faults. b[15:1] Reserved Always Returns 0
FAULT_LA: Latched Fault Register - Read
BIT(s) b[0] b[1] b[2] b[3] b[4] b[5] b[6] b[7] b[8] b[9] b[10] b[11] b[12] b[13] SYMBOL Fault_la_ch0_a_ov Fault_la_ch0_a_uv Fault_la_ch0_a_idac Fault_la_ch0_b_ov Fault_la_ch0_b_uv Fault_la_ch1_a_ov Fault_la_ch1_a_uv Fault_la_ch1_a_idac Fault_la_ch1_b_ov Fault_la_ch1_b_uv Fault_la_vdd_ov Fault_la_vdd_uv Fault_la_v12_ov Fault_la_v12_uv Always Returns 0 b[6] b[7] Io_alertb Io_alertb_enb OPERATION 0 = The associated channel is clear of faults. 1 = The associated channel has faulted and is enabled. The latched faults are set and held when the associated instantaneous fault channel has faulted with faults enabled. Clearing the enable bit for the associated channel in FAULT_EN will immediately clear its corresponding latched fault bit. All latched channel faults are cleared when this register is read. They may be set again if the instantaneous fault condition and fault_en have not changed. b[4] Io_gpio_0 b[3:2] Io_cfg_1[1:0]
b[15:14] Reserved
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IO: Input/Output Data and General Purpose Control Register - Read/Write unless specified otherwise.
BIT(s) b[1:0] SYMBOL Io_cfg_0[1:0] OPERATION Io_cfg_0[1:0] is used to configure the function of the GPIO_0 pin and IO(Io_gpio_0). 00: Io_gpio_0 = GPIO_0 = Power_good. Power_ good asserts high if there are no instantaneous over-voltage or under-voltage faults. 01: Io_gpio_0 = GPIO_0 = Power_good_bar. Power_good_bar is the complement of Power_good. 10: GPIO_0 is a general-purpose open-drain output and mirrors the value written to Io_gpio_0 (default). 11: GPIO_0 is a general-purpose digital input with Io_gpio_0 = GPIO_0 Io_cfg_1[1:0] is used to configure the function of the GPIO_1 pin and IO(Io_gpio_1). 00: Io_gpio_1 = GPIO_1 = Idac_fault. Idac_fault asserts if either IDAC value is faulted (Chn_idac[7:0] = 8'h00 or 8'hff) 01: Io_gpio_1 = GPIO_1 = Idac_fault_bar. Idac_fault_bar is the complement of Idac_fault. 10 = GPIO_1 is a general-purpose opendrain output and mirrors the value written to Io_gpio_1 (default). 11 = GPIO_1 is a general-purpose digital input with Io_gpio_1 = GPIO_1 See Io_cfg_0. If the GPIO_CFG pin is pulled-high during a power on reset, Io_gpio_0 is cleared and the GPIO_0 open-drain output will assert low. See Io_cfg_1. If the GPIO_CFG pin is pulled-high during a power on reset, Io_gpio_1 is cleared and the GPIO_1 open-drain output will assert low. Mirrors the value of the ALERT pin. Read only. 1 = ALERT pin never asserts (default). 0 = ALERT pin asserts low when one or more FAULT_LA bits are set. b[8] Io_i2c_adc_ wen 1 = Special test mode that inhibits ADC from writing to ADC result register and allows user to update registers over the I2C serial interface. 0 = Normal operation (default). b[9] Io_gpio_cfg Read only. GPIO_CFG digital input and opendrain output. Reading this bit returns the current state of the GPIO_CFG pin voltage. Writing a 1 to this bit will start tracking all enabled channels. Returns a 1 when tracking is pending (LTC2970-1). Reserved on LTC2970 and always returns 0. Always Returns 0
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b[5]
Io_gpio_1
b[10]
Io_track_start
b[15:11] Reserved
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LTC2970/LTC2970-1 OPERATIO
4. Detailed I2C Command Register Descriptions (Cont.)
ADC_MON: ADC Monitoring Mux Control Register - Read/Write
BIT(s) b[0] b[1] b[2] b[3] b[4] b[5] b[6] b[15:7] SYMBOL Adc_mon_vdd Adc_mon_v12 Adc_mon_ch0_a Adc_mon_ch0_b Adc_mon_ch1_a Adc_mon_ch1_b Adc_mon_temp Reserved Always Returns 0 b[15] Vdd_adc_new V12_adc_new Ch0_a_adc_new Ch0_b_adc_new Ch1_a_adc_new Ch1_b_adc_new Temp_adc_new OPERATION 0 = ADC will not convert associated channel. (Default) 1 = ADC will continuously convert associated channel.
SYNC: Tracking Synchronization Control Register - Read/Write LTC2970-1 Only
BIT(s) b[0] SYMBOL Sync_track OPERATION Write 0 = Do not synchronize. 1 = Synchronize all tracking enabled registers to the same starting point. Read 0 = The LTC2970-1 is not synchronized for tracking (default). 1 = The LTC2970-1 is synchronized for tracking. Use of the global address will allow the synchronization status of multiple LTC2970-1s to be verified in a single read; since a one can only be returned if all LTC2970-1s are synchronized. The IO_track_start command may then be issued with the same global address to begin synchronized tracking across multiple ICs. b[15:1] Reserved Always Returns 0
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VDD_ADC, V12_ADC, CH0_A_ADC, CH0_B_ADC, CH1_A_ADC, CH1_B_ADC, and TEMP_ADC: ADC Conversion Result Registers - Read Only Unless Specified Otherwise
BIT(s) b[14:0] SYMBOL Vdd_adc[14:0] V12_adc[14:0] Ch0_a_adc[14:0] Ch0_b_adc[14:0] Ch1_a_adc[14:0] Ch1_b_adc[14:0] Temp_adc[14:0] OPERATION Measured data from ADC conversion. 'h4000 corresponds to negative fullscale input voltage. 'h0000 corresponds to 0V. 'h3fff corresponds to full-scale input voltage. 2's complement format, b[14] = sign. Read/Write when Io_i2c_adc_wen = 1. Default value is undefined. 1 = The ADC has updated the associated result register since the last time the data was read. 0 = Previously read data. (Default)
VDD_OV, V12_OV, CH0_A_OV, CH0_B_OV, CH1_A_OV, CH1_B_ OV: Over Voltage Limit Registers - Read/Write
BIT(s) b[14:0] SYMBOL Vdd_ov[14:0] V12_ov[14:0] Ch0_a_ov[14:0] Ch0_b_ov[14:0] Ch1_a_ov[14:0] Ch1_b_ov[14:0] b[15] Reserved OPERATION ADC over-voltage threshold limit. The associated instantaneous over voltage fault is asserted if the channel's ADC result is greater than this limit. Code 'h3fff disables OV threshold detect feature for that channel. 2's complement format, b[14] = sign. Default value is undefined. Always Returns 0
VDD_UV, V12_UV, CH0_A_UV, CH0_B_UV, CH1_A_UV, CH1_B_ UV: Under Voltage Limit Registers - Read/Write
BIT(s) b[14:0] SYMBOL Vdd_uv[14:0] V12_uv[14:0] Ch0_a_uv[14:0] Ch0_b_uv[14:0] Ch1_a_uv[14:0] Ch1_b_uv[14:0] b[15] Reserved OPERATION ADC under-voltage threshold limit. The associated instantaneous under voltage fault is asserted if the channel's ADC result is greater than this limit. Code 'h4000 disables UV threshold detect feature for that channel. 2's complement format, b[14] = sign. Default value is undefined. Always Returns 0
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LTC2970/LTC2970-1 OPERATIO
4. Detailed I2C Command Register Descriptions (Cont.)
CH0_A_SERVO, CH1_A_SERVO: Voltage Servo Control Registers - Read/Write
BIT(s) b[14:0] SYMBOL Ch0_a_servo[14:0] Ch1_a_servo[14:0] OPERATION During servo operation Chn_a_idac[7:0] output current is stepped to force Chn_a_adc[14:0] code to equal target code stored in Chn_a_servo[14:0]. 2's complement format, b[14] = sign Default value is undefined. b[15] Ch0_a_servo_en Ch1_a_servo_en 0 = Chn_a servo disabled (default). 1 = Chn_a servo enabled. b[11] Ch0_a_idac_servo_repeat Ch1_a_idac_servo_repeat
CH0_A_IDAC, CH1_A_IDAC: IDAC Control/Data Registers - Read/Write
BIT(s) b[7:0] b[8] SYMBOL Ch0_a_idac[7:0] Ch1_a_idac[7:0] Ch0_a_idac_en Ch1_a_idac_en 0 = VOUTn output tri-stated. 1 = VOUTn output enabled. There are two ways to enable VOUTn. 1) When Chn_a_idac_en is set high with Chn_a_idac_con low, the LTC2970 will perform a soft connect. During a soft connect, the VOUTn voltage buffer output will not be connected to the VOUTn pin until the internal algorithm has servo'd the voltage at the IDACn pin to match the VOUTn pin voltage. Resolution is one Chn_a_idac LSB. 2) When Chn_a_idac_en is enabled with Chn_a_idac_con high, the LTC2970 will perform a hard connect. The VOUTn voltage buffer will be immediately connected to the VOUTn pin. b[9] Ch0_a_idac_con Ch1_a_idac_con 0 = VOUTn is not enabled or has been enabled but is not yet connected to the output of the CHn voltage buffer. (Default) 1 = VOUTn is enabled and has been connected to the output of the CHn voltage buffer. See Chn_a_idac_en for additional information. OPERATION Chn_a IDAC data value.
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b[10] Ch0_a_idac_pol Ch1_a_idac_pol 0 = Use this setting when increasing VOUTn causes (VINn_AP-VINn_AM) to decrease. Inverting configuration common to DC/DC converters with external feedback networks. 1 = Use this setting when increasing VOUTn causes (VINn_AP-VINn_AM) to increase. Non-inverting configuration common to DC/DC converters with trim pins. 0 = During servo operation, servo Chn_a until the measured result is stable and matches the target code. 1 = During servo operation, continuously servo Chn_a to the target code. b[15:12] Reserved Always Returns 0
CH0_A_IDAC_TRACK and CH1_A_IDAC_TRACK: IDAC Tracking data and control registers - Read/Write LTC2970-1 Only
BIT(s) b[7:0] SYMBOL Ch0_a_idac_ track[7:0] Ch1_a_idac_ track[7:0] b[8] b[15:9] OPERATION Final target value for of Chn_a_ idac[7:0]. During tracking, Chn_a_ idac[7:0] is incremented/decremented by 1 until it is equal to this value.
Ch0_a_idac_track_en 0 = inhibit tracking of Chn_a_idac[7:0]. Ch1_a_idac_track_en 1 = enable tracking of Chn_a_idac[7:0] Reserved Always Returns 0
CH0_A_DELAY_TRACK and CH1_A_DELAY_TRACK: IDAC Tracking delay register - Read/Write LTC2970-1 Only
BIT(s) b[9:0] b[1510] SYMBOL Ch0_a_delay_track[9:0] Ch1_a_delay_track[9:0] Reserved OPERATION Delay used to synchronize or offset tracking events. Always Returns 0
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LTC2970/LTC2970-1 OPERATIO
5. Soft Connecting the LTC2970 to the Power Supply Feedback Node The soft connect feature allows the LTC2970 to connect to the power supply's feedback node with minimal disturbance to the supply's output voltage. This is accomplished by comparing the buffered voltage of IOUTn to the voltage at VOUTn and incrementing or decrementing Chn_a_idac[7:0] until the comparator output (COMPn) changes. The value of Chn_a_idac[7:0] when the comparator transitions is the appropriate value for a soft connect. The voltage buffer output is only connected to VOUTn if the IDAC reaches this soft connect value without generating an instantaneous IDAC fault (Fault_chn_a_idac). Soft-Connect Procedure: Determine the appropriate polarity for Chn_a_idac_pol. Select Chn_a_idac_pol = 1 if incrementing VOUTn causes differential voltage (VINn_AP - VINn_AM) to increase. When properly programmed, lowering the value in Chn_ a_idac[7:0] will always cause the output of the controlled power supply to decrease. Ensure that the channel's IDAC is not currently enabled for connection, i.e., the Chn_a_idac_en bit must be 0. Update CHn_A_IDAC() with Chn_a_idac_pol, Chn_a_idac_ con = 0, Chn_a_idac_en = 1, and Chn_a_idac[7:0] = 0x80. The value programmed into Chn_a_idac[7:0] is ignored and Chn_a_idac[7:0] is initially set to 8'h80. The LTC2970 will now ramp Chn_a_idac[7:0] while monitoring the output of the soft connect comparator. If the soft connect comparator trips, the LTC2970 will connect the output of VBUFn to VOUTn and set Chn_a_idac_con high. If the soft connect comparator does not trip before the IDAC value reaches `h00 or `hFF, then the soft connection will fail, an IDAC fault will be indicated (Fault_chn_a_idac), and Chn_a_idac_con will remain low. Soft-Connect Rules: When both channels are requesting a soft connect, channel 0 has priority. Soft connect requests will be ignored and the user will not be able to change Chn_a_idac_pol or Chn_a_idac[7:0] if the LTC2970 is servicing a previously issued soft connect
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on that channel or the previously issued soft connect failed with an IDAC fault (Fault_chn_a_idac = 1). Recall that the Chn_a_idac_en bit must initially have been set to 0. LTC2970-1 Only: Soft connect requests will be ignored and the user will not be able to change Chn_a_idac_pol or Chn_a_idac[7:0] if GPIO_CFG is high and either GPIO_0 or GPIO_1 are high. LTC2970-1 Only: Soft connect requests will be ignored and the user will not be able to change the Chn_a_idac_pol bit if there is a pending tracking operation. 6. Hard Connecting the LTC2970 to the Power Supply Trim Pin The hard connect feature allows the LTC2970 to bypass the soft connect algorithm and connect directly to the power supply's feedback node using the value programmed into Chn_a_idac[7:0]. This feature is useful for systems that have calculated or measured an acceptable voltage at which to connect the IDAC's buffered voltage VBUFn to VOUTn. Hard Connect Procedure: Determine the appropriate polarity for Chn_a_idac_pol. Select Chn_a_idac_pol = 1 if incrementing VOUTn causes (VINn_AP - VINn_AP) to increase. When properly programmed, lowering the value in the IDAC will always cause the output of the controlled power supply to decrease. Determine the value for Chn_a_idac[7:0]. The values `h00 or `hff are allowed, but they will trip the IDAC's fault bit (Fault_chn_a_idac = 1). When the IDAC is already connected, the value Chn_a_ idac[7:0] and Chn_a_idac_pol will be programmed into the IDAC provided all other conditions are met. See "Programming a Previously Connected Current DAC" for details Update CHn_A_IDAC() with Chn_a_idac_pol, Chn_a_idac_ con = 1, Chn_a_idac_en = 1, and Chn_a_idac[7:0]. Hard Connect Rules: Hard connect requests will be ignored and the user will not be able to change Chn_a_idac_pol, Chn_a_idac_con or Chn_a_idac[7:0] if the LTC2970 is servicing a previously issued soft connect on that channel or the previously issued
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LTC2970/LTC2970-1 OPERATIO
soft connect failed with an IDAC fault (Fault_chn_a_idac = 1). Recall that a new hard connection requires the previous value of Chn_a_idac_en = 0. LTC2970-1 Only: Hard connect requests will be ignored and the user will not be able to change Chn_a_idac_pol, Chn_a_idac_con or Chn_a_idac[7:0] if GPIO_CFG is high and either GPIO_0 or GPIO_1 are high. LTC2970-1 Only: Hard connect requests will be ignored and the user will not be able to change Chn_a_idac_pol, Chn_a_ idac_con or Chn_a_idac[7:0] if there is a pending tracking operation. 7. Programming a Previously Connected IDAC The LTC2970 IDAC's may be programmed after they have been connected with a soft connect or a hard connect provided a servo operation is not enabled on the associated channel. Procedure: Determine the value for Chn_a_idac[7:0]. The values `h00 or `hff are allowed, but will trip the IDAC's fault bit (Fault_chn_a_idac = 1). Verify that the IDAC is already connected, and that Chn_a_idac_con is high. Ensure that servo mode is not enabled for the channel being programmed. Chn_a_servo_en must be low. This requirement prevents the user from interfering with a previously requested servo operation. Update the CHn_A_IDAC() register with Chn_a_idac_pol, Chn_a_idac_con = 1, Chn_a_idac_en = 1, and Chn_a_ idac[7:0]. Note: Care should be taken to preserve the current value of the Chn_a_idac_pol bit, since the LTC2970 does not prevent the user from changing this value when writing to the IDAC control registers. Rules: Setting Chn_a_idac_con to zero will not disconnect the DAC unless Chn_a_idac_en is also set low. All Hard Connect rules apply.
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8. Disconnecting the LTC2970 from the Power Supply Trim Pin VOUTn can be placed in a high impedance state simply by clearing the Chn_a_idac_en bit. In order to minimize the resulting disturbance to the power supply voltage, the IDAC code should not be changed from its current value when clearing the Chn_a_idac_en bit. This is not an issue if the channel's associated servo_en bit is high. Disconnect Procedure: Update CHn_IDAC() with Chn_a_idac_en set low. The LTC2970 will immediately disconnect the buffered IOUTn from VOUTn. Disconnect Rules: Clearing Chn_a_idac_con with Chn_a_idac_en high will not disconnect the IDAC. Only setting Chn_a_idac_en low will clear Chn_a_idac_con. LTC2970-1 Only: Chn_a_idac_en may not be changed if the feedback node connection is configured for tracking. Tracking is enabled when GPIO_CFG is high and either GPIO_0 or GPIO_1 are high. 9. Tracking Power Supplies Overview (LTC2970-1 Only) The LTC2970-1 tracking feature allows the I2C interface to initiate a controlled power up or power down of two or more supplies (Figure 2 shows a typical LTC2970-1 application circuit). Multiple LTC2970-1's with different addresses may be simultaneously programmed using the LTC2970 group address and the SYNC() command. Tracking is enabled when GPIO_CFG is pulled high and either GPIO_0 or GPIO_1 are high. 10. Tracking Power Supplies On (LTC2970-1 Only) The LTC2970-1 tracking feature allows the I2C to initiate a controlled power up of two or more supplies. Procedure: This procedure describes all the steps necessary to track up two or more power supplies. Steps that require I2C interaction are prefixed with the required I2C command function. Power-up the LTC2970-1 with GPIO_CFG pulled high.
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LTC2970/LTC2970-1 OPERATIO
This causes open-drain outputs GPIO_1 and GPIO_0 to automatically pull the power supplies' run/soft-start pins to ground. CHn_A_IDAC(): Hard connect Chn_a_idac[7:0] with a value that forces the power supplies off when GPIO_CFG = 1. Verify that Chn_a_idac_pol is at the appropriate value. CHn_A_IDAC_TRACK(): Set Chn_a_idac_track_en = 1, and set the Chn_a_idac_track[7:0] target value to the code that causes VOUTn to most closely approximate the corresponding power supply's feedback node voltage when it is in regulation. CHn_A_DELAY_TRACK(): Set the value by which the incrementing of IDACn should be delayed with respect to the start of tracking event. This controls whether the power supplies track up coincidentally or sequentially. IO(): Release the run/soft-start pins by programming io_gpio_n = 1. This will enable the power supplies without allowing their outputs to move since these are held off by Chn_a_idac[7:0]. Wait until power supplies have had sufficient time to start running before starting tracking. SYNC(): Optional command that allows multiple LTC29701's to be synchronized for tracking. Writing Sync_track = 1 will allow the LTC2970-1 to finish its current ADC conversion before having it wait to receive io_track_start = 1. The LTC2970-1 will timeout this wait command after tTIMEOUT_SYNC. Reading back Sync_track = 1 using the global address will ensure all LTC2970-1's are synchronized before proceeding with the tracking operation. IO(): Set Io_track_start = 1 and keep the run/soft-start pins enabled. Use the global I2C address to simultaneously track up power supplies across multiple LTC2970-1's. LTC2970-1 response: For each tracking enabled channel, the LTC2970-1 will decrement the CHn_A_delay_track counter at a rate of tDEC_TRACK. As soon as a channel's tracking counter reaches zero, the LTC2970-1 will begin stepping the value of Chn_a_idac[7:0] by one count until the final value of Chn_a_idac_track[7:0] is reached, at which point Chn_a_idac_track_en is de-asserted. When the final value is reached for all channels, GPIO_CFG is asserted low. After a time delay of tHOLD_TRACK, Chn_a_idac_en is de-asserted.
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Power-Up Tracking Rules: Tracking cannot begin if Chn_a_idac_con is not connected. This condition is met when the previous procedure is followed. Chn_a_idac_track_pol, Chn_a_idac_track_en, and ch0_ idac[7:0] updates will be ignored after IO(Io_track_start) is asserted until tracking is complete or whenever tracking is pending, i.e., GPIO_CFG pulled high with either GPIO_0 or GPIO_1 asserted pulled high. 11. Tracking Power Supplies Off (LTC2970-1 Only) The LTC2970-1 tracking feature allows the I2C to initiate a controlled power down of two or more supplies. Procedure: This procedure describes all steps necessary to track down two or more power supplies. Steps that require I2C interaction are prefixed with the required I2C command function. CHn_IDAC(): Disable the IDAC's for each tracking enabled channel (Chn_a_idac_en = 0). Ensure Chn_a_idac_pol is at the appropriate value. CHn_IDAC_TRACK(): Select the channels to be tracked by setting Chn_a_idac_track_en = 1, and set the target value for each Chn_a_idac_track[7:0] to that which forces the supply off. CHn_A_DELAY_TRACK(): Set the value by which the decrementing of that channel's DAC should be delayed with respect to the start of the tracking event. This controls whether the supplies track down coincidentally or sequentially. SYNC(): Optional command that allows multiple LTC29701's to be synchronized for tracking. Writing Sync_track = 1 will allow the LTC2970-1 to finish its current ADC conversion before having it wait to receive io_track_start = 1. The LTC2970-1 will timeout this wait command after tTIMEOUT_SYNC. Reading back Sync_track = 1 using the global address will ensure all LTC2970's are synchronized before proceeding with the tracking operation. IO(): Set Io_track_start = 1. Use the global I2C address to simultaneously track down power supplies across multiple LTC2970's.
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LTC2970/LTC2970-1 OPERATIO
LTC2970-1 response: Each tracking enabled channel is soft connected. The GPIO_CFG pin is released allowing it to be pulled high. The LTC2970-1 waits tSETUP_TRACK to allow GPIO_CFG to settle. For each tracking enabled channel, the Chn_a_delay_track counter is decremented at a rate of tDEC_TRACK. As soon as a channel's tracking counter reaches zero, the LTC2970-1 will begin stepping the value of Chn_a_idac[7:0] by one count until the final value of Chn_a_idac_track[7:0] is reached. The tracking enable bit is then cleared for both channels (Chn_a_idac_track_en = 0). IO(): The I2C interface may then be used to set GPIO_1 and GPIO_0 low, disabling the power supplies. Power Down Tracking Rules: Power down tracking requests will be ignored until the user has disabled the IDAC's by setting Chn_a_idac_en = 0 for each tracking enabled channel. Chn_a_idac_track_pol, Chn_a_idac_track_en, and ch0_ idac[7:0] updates will be ignored after IO(IO_track_start) is asserted until tracking is complete and whenever tracking range is configured; (GPIO_CFG high with either GPIO_0 or GPIO_1 asserted high). 12. Continuous Power Supply Voltage Servo The continuous voltage servo feature allows the LTC2970 to servo an external power supply to a programmed value. The voltage of the external supply is monitored over Chn_A_ADC and compared to a target value stored in Chn_a_servo. After each conversion, Chn_A_IDAC is incremented by 1, decremented by 1, or held; whichever brings or keeps the measured voltage closer to the targeted servo value. Procedure: Follow procedure for hard connecting or soft connecting the LTC2970 to power supply trim pin; when updating CHn_A_IDAC(), Chn_a_idac_servo_repeat should be asserted high. The servo channel's IDAC must be enabled before Chn_A_servo_en can be set high.
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Determine the target servo voltage, Chn_a_servo[14:0]. Update CHn_A_SERVO() with Chn_a_servo_en = 1, and Chn_a_servo[14:0]. Update CHn_A_IDAC() with Chn_a_idac_servo_repeat = 1. This step may be skipped if Chn_a_idac_servo_repeat was set high during the soft or hard connect procedure. LTC2970 response: The LTC2970 will continuously increment, decrement or hold Chn_a_idac[7:0] in order to match the measured value of (VINn_AP-VINn_AM) to Chn_a_servo[14:0]. Whenever the CHn_A_SERVO() register is updated an internal flag is cleared indicating that a successful servo has not been completed. This internal flag, Chn_a_servo_done, initially causes the ADC to operate in an accelerated 12-bit mode. Once the channel reaches the servo target, the ADC switches back to 14-bit mode for two conversions before asserting Chn_a_servo_done high. In continuous voltage servo mode the Chn_a_servo_done flags allow the initial servo target to be reached quickly. During this time, ADC conversions for all non-servo channels are temporarily inhibited. Rules: The IDAC associated with the servo channel must be enabled. If Chn_a_idac_en is low the servo enable bit Chn_a_servo_en is always forced low. The IDAC associated with the servo channel must be connected (Chn_a_idac_con = 1). An IDAC fault may be generated during a continuous servo operation. The LTC2970 will report the fault and continue trying to servo that channel. LTC2970-1 Only: There must be no pending tracking commands. A pending tracking command will clear Chn_a_servo_en. LTC2970-1 Only: The tracking range must not be enabled; (GPIO_CFG high with either GPIO_0 or GPIO_1 asserted high). An enabled tracking range will clear Chn_a_servo_en low.
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LTC2970/LTC2970-1 OPERATIO
13. One Time Power Supply Voltage Servo The one time voltage servo feature allows the LTC2970 to servo an external power supply to a programmed value and then stop updating the IDAC once the target value has been reached. Procedure: Follow procedure for hard connecting or soft connecting the LTC2970 to power supply trim pin; when updating CHn_A_IDAC(), Chn_a_idac_servo_repeat should be deasserted low. The servo channel's IDAC must be enabled before Chn_a_servo_en may be set high. Update CHn_A_IDAC() with Chn_a_idac_servo_repeat = 0. This step may be skipped if Chn_a_idac_servo_repeat was cleared low during the soft or hard connect procedure. Update FAULT_EN() with Fault_en_chn_a_servo = 0. This prevents the LTC2970 from reinitiating a servo after an over-voltage or under-voltage fault. Determine the target servo voltage, Chn_a_servo[14:0]. Update CHn_A_SERVO() register with Chn_a_servo_en = 1, and Chn_a_servo[14:0]. LTC2970 response: The LTC2970 will increment, decrement or hold Chn_a_idac[7:0] in order to match the measured value of (VINn_AP-VINn_AM) to Chn_a_servo[14:0]. The servo procedure will end when the internal Chn_a_servo_ done flag is set (see "Continuous Power Supply Voltage Servo"). At this point the IDAC is either programmed to the appropriate servo value or faulted. Rules: All "Continuous Power Supply Voltage Servo" rules apply. 14. One Time Power Supply Voltage Servo with Repeat On Fault The LTC2970 one time voltage servo feature may be modified to allow the LTC2970 to perform an additional power supply servo operation after an under-voltage or over-voltage fault is detected on the servo channel.
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Procedure: Follow procedure outlined for "One Time Power Supply Voltage Servo". Update FAULT_EN() with Fault_en_chn_a_servo = 1. Enable detection of the appropriate instantaneous faults for all servo channels; see "Generating and Monitoring Instantaneous Faults". LTC2970 response: Any time an instantaneous undervoltage or over-voltage fault is detected on the servo channel (Fault_ov_a_chn or Fault_uv_a_chn), the internal Chn_a_servo_done flag for that channel is cleared, and the LTC2970 will perform a complete one time servo. This allows the LTC2970 to precisely restore the power supply to the target servo value, after it has drifted beyond a user defined operating window. Rules: All "Continuous Power Supply Voltage Servo" rules apply. During a permanent under-voltage or over-voltage fault the LTC2970 will continuously try to correct the faulted channel, after each failed attempt all other channels that need monitoring by the ADC will be serviced. 15. Configuring ADC to Monitor Input Channels and Internal Temperature Sensor The LTC2970 is able to perform ADC conversions on any combination of seven different input channels. A channel is converted if its associated ADC_MON() bit is set high. Refer to Table 7 for details. Procedure: Update ADC_MON() with the control bit of each channel that is to be monitored set high. LTC2970 response: All enabled channels will be sequentially converted. The result of the most recent conversion may be read from the ADC result register. Each time a conversion is completed the new data bit associated with the result register is asserted high. The new data bit is
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LTC2970/LTC2970-1 OPERATIO
Table 7. LTC2970 ADC Conversion and Fault Limit Registers
INPUT CHANNEL TEMPERATURE VIN1_BP-VIN1_BM VIN1_AP-VIN1_AM VIN0_BP-VIN0_BM VIN0_AP-VIN0_AM 12VIN VDD ADC_MON() CONTROL BIT Adc_mon_temp Adc_mon_b_ch1 Adc_mon_a_ch1 Adc_mon_b_ch0 Adc_mon_a_ch0 Adc_mon_v12 Adc_mon_vdd ADC RESULT REGISTER (2s COMPLEMENT) Temp_adc[14:0] Ch1_b_adc[14:0] Ch1_a_adc[14:0] Ch0_b_adc[14:0] Ch0_a_adc[14:0] V12_adc[14:0] Vdd_adc[14:0] OV FAULT REGISTER (2s COMPLEMENT) Ch1_b_ov[14:0] Ch1_a_ov[14:0] Ch0_b_ov[14:0] Ch0_a_ov[14:0] V12_ov[14:0] Vdd_ov[14:0] UV FAULT REGISTER (2s COMPLEMENT) Ch1_b_uv[14:0] Ch1_a_uv[14:0] Ch0_b_uv[14:0] Ch0_a_uv[14:0] V12_uv[14:0] Vdd_uv[14:0]
reset each time the result register is read. This provides a simple mechanism for supervisory software to determine if a new conversion has been completed since data was last read. Rules: The LTC2970 assigns priority to ADC conversions of CH1_A_ADC and CH0_A_ADC when these channels are in their initial fast servo mode. The IO() register control bit Io_i2c_adc_wen must be low in order for ADC conversions to be performed. LTC2970-1 Only: ADC conversions are suspended during any pending tracking requests.
Table 8. LTC2970 Fault Reporting Bits and Conditions
CONDITION THAT GENERATES AN INSTANTANEOUS FAULT V12_adc[14:0] < V12_uv[14:0] V12_adc[14:0] > V12_ov[14:0] Vdd_adc[14:0] < Vdd_uv[14:0] Vdd_adc[14:0] > Vdd_ov[14:0] Ch1_b_adc[14:0] < Ch1_b_uv[14:0] Ch1_b_adc[14:0] > Ch1_b_ov[14:0] Idac_a_ch1[7:0] = 8'ff or 8'h00 Ch1_a_adc[14:0] < Ch1_a_uv[14:0] Ch1_a_adc[14:0] > Ch1_a_ov[14:0] Ch0_b_adc[14:0] < Ch0_b_uv[14:0] Ch0_b_adc[14:0] > Ch0_b_ov[14:0] Idac_a_ch0[7:0] = 8'ff or 8'h00 Ch0_a_adc[14:0] < Ch0_a_uv[14:0] Ch0_a_adc[14:0] > Ch0_a_ov[14:0]
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16. Generating and Monitoring Instantaneous Faults The LTC2970 supports fourteen different types of instantaneous faults. These faults together with the conditions that trigger them are defined in Table 8. There are six under-voltage faults, six over-voltage faults and two IDAC limit faults. The FAULT() command may be used to read the status of all instantaneous fault bits. The IO() command may be used to configure GPIO_0 and GPIO_1 to view voltage limit and IDAC faults respectively. The state of GPIO_0 and GPIO_1 may be read using IO().
FAULT() FAULT_EN() FAULT_LA() INSTANTANEOUS FAULT REPORTING ENABLE FOR LATCHED FAULT REPORTING LATCHED FAULT REPORTING Fault_v12_uv Fault_v12_ov Fault_vdd_uv Fault_vdd_ov Fault_ch1_b_uv Fault_ch1_b_ov Fault_ch1_a_idac Fault_ch1_a_uv Fault_ch1_a_ov Fault_ch0_b_uv Fault_ch0_b_ov Fault_ch0_a_idac Fault_ch0_a_uv Fault_ch0_a_ov Fault_en_v12_uv Fault_en_v12_ov Fault_en_vdd_uv Fault_en_vdd_ov Fault_en_ch1_b_uv Fault_en_ch1_b_ov Fault_en_ch1_a_idac Fault_en_ch1_a_uv Fault_en_ch1_a_ov Fault_en_ch0_b_uv Fault_en_ch0_b_ov Fault_en_ch0_a_idac Fault_en_ch0_a_uv Fault_en_ch0_a_ov Fault_la_v12_uv Fault_la_v12_ov Fault_la_vdd_uv Fault_la_vdd_ov Fault_la_ch1_b_uv Fault_la_ch1_b_ov Fault_la_ch1_a_idac Fault_la_ch1_a_uv Fault_la_ch1_a_ov Fault_la_ch0_b_uv Fault_la_ch0_b_ov Fault_la_ch0_a_idac Fault_la_ch0_a_uv Fault_la_ch0_a_ov
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Procedure: Update the over-voltage limit register with the value above which the ADC result should generate an over-voltage fault. Instantaneous over-voltage faults are updated after each ADC conversion. They are asserted high when the ADC result is greater than the over-voltage limit. They are cleared if the ADC result is less than or equal to the over-voltage limit. Setting the over-voltage limit to 14'h3fff inhibits instantaneous faults for the associated channel. Update the under-voltage limit register with the value below which the ADC result should generate an under-voltage fault. Instantaneous under-voltage faults are updated after each ADC conversion. They are asserted high when the ADC result is less than the under-voltage limit. They are cleared if the ADC result is greater than or equal to the under-voltage limit. Setting the over-voltage limit to 14'h4000 inhibits instantaneous faults for the associated channel. Update ADC_MON() control bits to allow ADC conversions on all channels that are to be monitored for over and under voltage limits. Instantaneous IDAC faults are polled after all ADC conversions are completed and set when the associated IDAC registers are at `h00 of `hff. Read FAULT() to view the value of all instantaneous faults. The IO(Io_cfg_0) command may be used to configure the GPIO_0 pin to output the internal Power_good flag. Power_good is asserted high if there are no instantaneous over-voltage or under-voltage faults. IO() may be used to read the value of Power_good through io_gpio_0. The IO(Io_cfg_1) command may be used to configure the GPIO_1 pin to output the internal Idac_fault flag. Idac_fault is asserted high if either IDAC value is faulted. IO() may be used to read the value of Idac_fault through io_gpio_1. Rules: The over-voltage and under-voltage limits must be initialized; they do not have a default value. All over-voltage limits, under-voltage limits and ADC results use 2's complement notation with bit position [14] of register [14:0] being used for the sign.
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Instantaneous Ch0_a and Ch1_a faults may be used to trigger a servo on fault event. Over-voltage and under-voltage faults require that the associated ADC_MON control bit be asserted high for instantaneous fault detection to be updated. 17. Generating and Monitoring Latched Faults The LTC2970 is able to selectively latch instantaneous faults in the latched fault register FAULT_LA. Each instantaneous fault has an associated latched fault bit in FAULT_LA and a fault enable bit in FAULT_EN; (see Table 8) for details. When an instantaneous fault enable bit is high, any event that sets the instantaneous fault will simultaneously set the latched fault. The latched fault will remain set even if conditions permit the instantaneous fault to be cleared. The latched faults are immediately cleared whenever the associated fault enable bit is cleared. All latched faults are also cleared when the latched fault register is read over FAULT_LA(). The FAULT_INDEX() command may be read to determine if any latched faults are asserted. Reading FAULT_INDEX() does not clear latched faults. The ALERT output may also be configured to view whether any latched faults are asserted. Procedure: Follow procedure for generating instantaneous faults. Write FAULT_EN() to enable any combination of latched faults. Read FAULT_INDEX() to determine if any latched faults are asserted without clearing latched faults. Read FAULT_LA() to monitor all latched faults. Reading FAULT_LA() will clear all latched faults. These will remain clear until the next time the LTC2970 polls and sets an associated instantaneous fault. Setting IO(Io_alert_enb) low will cause ALERT to be asserted low whenever any one of the fourteen latched faults is asserted high. The value of the ALERT pin may also be read through IO(Alertb).
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Rules: See "Generating and Monitoring Instantaneous Faults". 18. General Purpose Input/Output Pins The GPIO_0 and GPIO_1 may be used to: (1) monitor instantaneous faults (see "Generating and Monitoring Instantaneous faults"); (2) control switcher run/start pins during tracking (see "Tracking Power Supplies Overview"); or (3) provide general purpose input/output pins. Procedure: To program GPIO_n as an open drain output set Io_cfg_n = 2'b10. The value written to lo_gpio_n will be output over GPIO_n. To program GPIO_n as an input set Io_cfg_n = 2'b11. The value of GPIO_n may now be read through lo_gpio_n.
APPLICATIO S I FOR ATIO
Margining DC/DC Converters with External Feedback Resistors
R50
Figure 1 shows a typical application circuit for margining a power supply with an external feedback network. The VIN0_AP and VIN0_AM differential inputs sense the load voltage directly, and differential inputs VIN0_BP and VIN0_BM are connected across load current sense resistor R50. A correction voltage is developed at the IOUT0 pin by sourcing IDAC0's current into resistor R40. R40 is Kelvin connected to the point-of-load GND in order to isolate VIOUT0 from ground bounce due to load current changes. VIOUT0 is replicated at VOUT0 by an on-chip, unity-gain voltage buffer. VOUT0 is then connected to the feedback node of the power supply through resistor R30. The feedback node can be isolated from the DAC's correction voltage by placing the VOUT0 pin in high-impedance mode. Since the GPIO_CFG pin is pulled-up to VDD, the LTC2970's GPIO_0 pin will automatically hold the power supply's RUN/SS pin low after power-up until the I2C interface releases it.
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Rules: The power on reset configurations for GPIO_0 and GPIO_1 are output pins with a value equal to the complement of the GPIO_CFG level. 19. Advanced Development Features The internal ADC may be disabled with the ADC result registers accepting written I2C data. This feature allows faults to be generated for diagnostic purposes, without having to generate an actual overvoltage or undervoltage event. Procedure: Set IO(Io_i2c_adc_wen) high to enable ADC result register writes and disable internal ADC updates. Rules: Io_i2c_adc_wen must be clear for normal operation.
8V TO 15V 0.1F VIN VDD 1/2 LTC2970 GPIO_CFG I+ I- DC/DC CONVERTER R30 R20 RUN/SS FB R10 GND SGND + LOAD VDC0 - IOUT0 R40 VIN0_AM REF 0.1F GPIO_0 VIN0_BM VIN0_BP VOUT0 VIN0_AP ALERT SCL SDA I2C BUS 0.1F VIN IN OUT GND ASEL0 ASEL1
29701 F01
Figure 1. Typical LTC2970 Application Circuit for DC/DC Converters with External Feedback Resistors
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4-Step Resistor Selection Procedure for DC/DC Converters with External Feedback Resistors The following 4-step procedure should be used to quickly calculate the resistor values shown for the Typical Application Circuit shown in Figure 1. 1. Assume values for feedback resistor R20 and the nominal DC/DC converter output voltage VDC0,NOM, and solve for R10. VDC0,NOM is the desired output voltage of the DC/DC converter when the LTC2970's VOUT0 pin is in a high impedance state. VFB0 is the voltage at the converter's feedback node when the loop is in regulation, and IFB0 is the feedback node's input current. R10 = R20 * VFB0 VDC,NOM - IFB0 * R20 - VFB0 (1)
2. Solve for the maximum value of R30 that yields the maximum required DC/DC converter output voltage VDC0,max. When VOUT0 is at 0V, the output of the DC/DC converter is at its maximum voltage. Note that the 10mV term corresponds to the maximum offset voltage of the IDAC 1X voltage buffer. R30 R20 * ( VFB - 10mV ) VDC,MAX - VDC,NOM (2)
3. Solve for the minimum value of R40 that's needed to yield the minimum required DC/DC converter output voltage VDC0,MIN. The DC/DC converter output voltage will be a minimum when IDAC0 is at its full-scale current. In order to guarantee that R40 is large enough, assume that IDAC0's full-scale current is at the datasheet minimum of 236A.
R40
( VDC,NOM - VDC,MIN ) * R30 + VFB + 10mV R20
236A
4. Re-calculate the minimum, nominal, and maximum DC/DC converter output voltages and the resulting margining resolution.
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R20 VDC0,NOM = VFB * 1+ + I * R20 R10 FB R20 * R30 (R40 * 236A - VFB0 - 10mV ) VDC0,MIN VDC0,NOM - VDC0,MAX VDC0,NOM + R20 * ( VFB0 - 10mV ) R30 (4) (5) (6) The margining resolution is bounded by: R20 * R40 * 276A volts/DAC LSB VRES R30 256 Margining DC/DC Converters with a TRIM Pin Figure 2 illustrates a typical application circuit for margining the output voltage of a DC/DC converter with a TRIM Pin. The LTC2970's VOUT0 pin connects directly to the TRIM pin through resistor R30 and the IOUT0 pin is terminated at the converter's point-of-load ground throught R40. Resistors R30 and R40 give this application circuit two separate degrees of freedom so that the margin-up and margin-down percentages can be specified independently of each other. Following power-up, the LTC2970's VOUT0 pin defaults to a high-impedance state. If the soft-connect feature is used,
8V TO 15V 0.1F 12VIN VIN VO+ 1/2 LTC2970 GPIO_CFG R30 TRIM DC/DC CONVERTER VSENSE+ + ON/OFF LOAD VDC0 - IOUT0 R40 VIN0_AM REF 0.1F GPIO_0 VOUT0 VIN0_AP ALERT SCL SDA I2C BUS VDD 0.1F
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(3)
VSENSE- VO-
GND ASEL0 ASEL1
29701 F02
Figure 2. LTC2970 Application Circuit for DC/DC Converters with a TRIM Pin
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LTC2970/LTC2970-1 APPLICATIO S I FOR ATIO
the LTC2970 will automatically find the IDAC code that most closely approximates the TRIM pin's open-circuit voltage before enabling VOUT0. Note: The relationship between VTRIM and the converter's output is typically non-inverting, so be sure to set the LTC2970's CH0_a_idac_pol bit to 1 in order to allow the voltage servo feature to function properly. DC/DC converters with a TRIM pin are usually margined high or low by connecting an external resistor between the TRIM pin and either the VSENSE+ or VSENSE- pin. The relationships between these resistors and the % change in the output voltage of the DC/DC converter are typically expressed as:
RTRIM _ DOWN = RTRIM _UP = RTRIM * VDC * (100 + UP %) RT RIM * 50 - RTRIM - UP % 2 * VREF * UP % RTRIM * 50 - RTRIM DOWN %
where RTRIM is the resistance looking into the TRIM pin, VREF is the TRIM pin's opern-circuit output voltage and VDC is the DC/DC converter's nominal output voltage. UP% and DOWN% denote the percentage change in the converter's output voltage when margining up or down respectively. 2-Step Resistor Selection Procedure for DC/DC Converters with a TRIM Pin
I2C BUS
The following two-step procedure should be used to calculate values for resistors R30 and R40 shown in Figure 2. 1. Solve for R30:
50 - DOWN % R30 RTRIM * DOWN %
2. Solve for R40:
UP % VREF * R40 1 + DOWN % 236 A
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Tracking with the LTC2970-1 A typical LTC2970-1 tracking application circuit is shown in Figure 3 (the sequence of events for tracking are described in sections 9 and 10 of the Operation section). The GPIO_0 and GPIO_1 pins are tied directly to their respective DC/DC converter RUN/SS pins. Since GPIO_CFG is pulled-up to VDD, the LTC2970-1 will automatically hold off the DC/DC converters after power-up by asserting open drain outputs GPIO_0 and GPIO_1 low. N-channel FETs Q10/11 and diodes D10/11 form unidirectional range switches around resistors R30A/31A while GPIO_CFG is high. These range switches allow the LTC2970-1's VOUT0 and VOUT1 pins to drive the converter outputs all the way to/from ground through resistors R30B/31B. When GPIO_CFG pulls low, N-channel FETs Q10 and Q11 will turn off. R30A/31A and R30B/31B then combine in series for normal margin operation. The 100k/0.1F low-pass filter in series with the gates of Q10/11 minimizes charge injection into the feedback nodes of the DC/DC converters when GPIO_CFG pulls low.
8V TO 15V 0.1F 12VIN VDD 10k GPIO_CFG 100k GPIO_0 LTC2970-1 Q10 VOUT0 R30A ALERT SCL SDA IOUT0 R30B R10 0.1F R40 R20 FB OUT VDC0 D10 RUN/SS IN VIN 0.1F Q10, Q11: 2N7002 D10, D11: MMBD4448V *SOME DETAILS OMITTED FOR CLARITY
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(8)
(9)
DC/DC CONVERTER
GPIO_1 D11 Q11 VOUT1 R31A R31B
RUN/SS
IN
VIN
DC/DC CONVERTER FB R21 OUT VDC1
R11
(10)
GND
IOUT1 R41
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Figure 3. LTC2970-1 Tracking Application Circuit
(11)
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LTC2970/LTC2970-1 APPLICATIO S I FOR ATIO
7-Step Procedure for Calculating Tracking Application Circuit Resistor Values, Counter Delay Values, and Terminal IDAC Codes The following 7-step procedure should be used to calculate the resistor values, tracking counter delays, and terminal IDAC codes for the Tracking Application Circuit shown in Figure 3. 1. Assume a value for R20 and solve for R21. VDCn,NOM is the output voltage of the DC/DC converter when the LTC2970's VOUTn pin is in a high impedance state. R21= R20 * VDC1,NOM VDC0,NOM (12)
2. Solve for R10 and R11. R1n = R2n VDCn,NOM - 1 V
FBn
3. Solve for R40 and R41. For simplicity, this procedure assumes that R40 = R41. VDCn,MAX and VDCn,MIN are the maximum and minimum converter output margin voltages, respectively. The value of R40 = R41 is constrained by: R40 = R41 (14) R30B R31B = R20 R21
VDCn,NOM - VDCn,MIN + 1 + 10mV VFBn * VDCn,MAX - VDCn,NOM 236A
( (
) )
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Due to the forward drop of diodes D10 and D11 (0.8V max), the minimum value for R40 = R41 from expression (14) may result in small or even negative values of R30 and R31 in Step 4. If this is the case, assume a minimum allowable value for R3nB, and use the following expression to calculate the minimum value R40 = R41: R40 = R41 R3nB R3nB VFBn * 1+ + + 0.8 V + 10mV R1n R2n 236A Note: Use the channel whose parameters yield the maximum value for R40 = R41. 4. Solve for R30B and R31B. Solve for the upper limits of R30B and R31B and then determine which resistor value constrains the maximum value of the other resistor using Equation 17. R3nB (15) (13)
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(R4n * 236A - VFBn - 0.8V - 10mV )
1 1 VFBn * + R1n R2n
(16)
(17)
5. Solve for R30A and R31A. R30A and R31A are constrained by: R3nA R2n R2n VDCn,MAX - VDCn,NOM 1+ R1n * VDCn,NOM - R3nB (18)
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LTC2970/LTC2970-1 APPLICATIO S I FOR ATIO
6. Solve for Channel 1's tracking counter delay relative to Channel 0, CH1_A_DELAY_TRACK(). CH1_ A _ DELAY _ TRACK() = R31B VDC1,NOM - VDC0,NOM * R21 (counts) 1A / count * R41 (19)
(
)
Note: VDCn,NOM is based on the final values of R2n and R1n. If the result for CH1_A_DELAY_TRACK() is less than 0, apply the unsigned result to the CH0_A_DELAY_TRACK() register. 7. Solve for the IDAC0 and IDAC1 terminal tracking codes, Chn_a_idac_track[7:0]. Chn _ a _ idac _ track[7 : 0] = VFBn 255 - (LSB's) 1A / LSB * R4n (20)
Note: This formula assumes that the Chn_a_idac_pol bit is set to 0. Margining Application Circuit Design Example Consider the LTC2970 application circuit shown in Figure 1. Channel 0 is a DC/DC converter whose output needs to be varied between 3.63V and 1.62V. VFB0 = 0.8V and assume that IFB0 = 0A. 1. Assume values for feedback resistor R20 and the nominal DC/DC converter output voltage VDC0,NOM, and solve for R10. Let VDC0,NOM = 2.625V (the average of 3.63V and 1.62V) and assume that R20 = 10k. From Equation 1: R10 = R20 * VFB0 = VDC,NOM - IFB0 * R20 - VFB0
10k * 0.8 V = 4, 384 2.625V - 0.8 V Let R10 = 4.37k (the nearest E192 series resistor value).
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2. Solve for the value of R30 that yields the maximum required DC/DC converter output voltage VDC0,MAX From Equation 2: R30 R20 * ( VFB - 10mV ) = VDC,MAX - VDC,NOM 10.0k * ( 0.8 V - 10mV ) = 7, 861 3.63V - 2.625V Let R30 = 7.68k. 3. Solve for the value of R40 that's needed to yield the minimum required DC/DC converter output voltage VDC0,MIN. From Equation 3: R40 = 236A .96 (2.625V - 1.62V ) * 710kk + 0.8V = 6, 780 236A
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( VDC,NOM - VDC,MIN ) * R30 + VFB R20
Let R40 = 6.81k. 4. Re-calculate the minimum, nominal, and maximum DC/DC converter output voltages and the resulting margining resolution. From Equations 4, 5, and 6: R20 VDC0,NOM = VFB * 1+ + I * R20 = R10 FB 10k 0.8 V * 1+ = 2.631V 4.37k VDC0,MIN < VDC0,NOM - R20 * ( 236A * R40 - VFB0 ) R30
10k * 7.68k (236A * 6.81k - 0.8V - 10mV ) = 1.59V VDC0,MIN < 2.631V -
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LTC2970/LTC2970-1 APPLICATIO S I FOR ATIO
VDC0,MAX > VDC0,NOM + R20 * ( VFB0 - 10mV ) R30
10k * 7.68k (0.8V - 10mV ) = 3.660V VDC0,MAX > 2.631V + From Equation 7, the margining resolution will be less than: R20 * R40 * 276A R30 VRES < = 256 10k * 6.65k * 276A 7.68k = 9.33mV/LSB 256 Margining DC/DC Converter with TRIM Pin Design Example The output voltage of the DC/DC converter in Figure 2 needs to be margined 10% about its nominal value. Assume that RTRIM = 10.22k and VREF = 1.225V. 1. Solve for R30 using Equation 10: 50 - DOWN % R30 RTRIM * %
DOWN
50 - 1 0 = 10 . 22k * = 40, 880 10 Let R30 = 39.2k. 2. Solve for R40 using Equations 11: UP % VREF * R40 1 + DOWN % 236 A 10 1 . 225V = 1+ * = 10, 381 10 236 A Let R40 = 10.5k.
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Tracking Application Circuit Design Example Consider the LTC2970-1 application circuit shown in Figure 3. Channel 0 is a 1.8V DC/DC converter while channel 1 is a 2.5V switching power supply. Both converters have a feedback node voltage of 0.8V and need to track on and off coincidentally. In addition, a margin range of +5% and -10% is required for each supply. 1. Assume a value for R20 and solve for R21. Let R20 = 5,970. From Equation 12: R21= R20 * VDC1,NOM VDC0,NOM = 5, 970 * 2.5V = 8, 292 1.8 V Let R21 = 8,250 (the nearest E192 Series resistor value). 2. Solve for R10 and R11. From Equation 13: R10 = R20 VDC0,NOM - 1 V
FB0
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=
5, 970 = 4, 776 1.8 V 0.8 V - 1
R11=
R21 VDC1,NOM - 1 V
FB1
=
8, 250 = 3, 882 2.5V 0.8 V - 1
Let R10 = 4,750 and R11 = 3,880. 3. Solve for R40 and R41. Assume that R40 = R41. R40 = R41 VDCn,NOM - VDCn,MIN VFBn * + 1 + 10mV VDCn,MAX - VDCn,NOM = 236A (1- 0.9) 0.8 V * + 1 + 10mV (1.05 - 1) = 10, 212 236A Let R40 = R41 = 10.5k
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( (
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LTC2970/LTC2970-1 APPLICATIO S I FOR ATIO
4. Solve for R30B and R31B.
(R40 * 236A - VFB0 - 0.8V - 10mV ) = R30B 1 1 + VFB0 * R10 R20 (10.5k * 236A - 0.8 V - 0.8 V - 10mV) = 2, 870 1 1 + 0.8 V * 4, 750 5, 970
R31B 1 1 VFB1 * + R11 R21 (10.5k * 236A - 0.8 V - 0.8 V - 10mV) = 2, 863 1 1 + 0.8 V * 3, 880 8, 250
(R41* 236A - VFB1 - 0.8V - 10mV ) =
For coincident tracking to occur Equation 17 also must be satisfied: R30B R31B = R20 R21 R30B = R31B = R31B 2, 863 * R20 = * 5, 970 = 2, 078 R21 8, 250 R30B 2, 870 * R21= * 8, 250 = 3, 957 R20 5, 970
Let R30B = 2,100 and R31B = 2,890. 5. Solve for R30A and R31A. Referring to Equation 18: R30 A R20 R20 VDC0,MAX - VDC0,NOM 1+ R10 * VDC0,NOM - R30B =
5, 970 - 2,100 = 50, 806 5, 970 1.05 - 1 1+ 4, 750 * 1
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R31A R21 R21 VDC1,MAX - VDC1,NOM 1+ R11 * VDC1,NOM - R31B = 8, 250 - 2, 890 = 49, 888 8, 250 1.05 - 1 1+ 3, 880 * 1 Let R30A = 49.9k and R31A = 48.7k. 6. Solve for Channel 1's tracking counter delay relative to Channel 0, CH1_A_DELAY_TRACK(). First, recalculate the values of VDCn,NOM based on the final values of R1n and R2n: R20 + I * R20 = VDC0,NOM = VFB * 1+ R10 FB 5, 970 + 0 = 1.805V 0.8 V * 1+ 4, 750 8, 250 + 0 = 2.501V VDC1,NOM = 0.8 V * 1+ 3, 880 Next, apply Equation 19: CH1_ A _ DELAY _ TRACK() = R31B VDC1,NOM - VDC0,NOM * R21 = 1A / count * R41 2 (2.501V - 1.805V ) * 8,,890 250 = 23 counts 1A / count * 10.5k
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LTC2970/LTC2970-1 APPLICATIO S I FOR ATIO
2.7 2.4 2.1 1.8 VOLTS 1.5 1.2 0.9 0.6 0.3 0 5ms/DIV
29701 F04
VDC1
VDC0
Figure 4. Tracking Design Example DC/DC Converter Output Waveforms
7. Solve for the IDAC0 and IDAC1 terminal tracking codes, Chn_a_idac_track[7:0]. Ch0 _ a _ idac[7 : 0] = Ch1_ a _ idac[7 : 0] = 0.8 V 255 - = 179 1A / LSB * 10.5k Figure 4 shows the DC/DC converter output voltages for this design example tracking-up and tracking-down. Negative Power Supply Application Circuit Figure 5 shows the LTC2970 controlling a negative power supply. The R10/R20 resistor divider translates the point of load voltage to the LTC2970's VIN0_A inputs while the VIN0_B inputs monitor the converter's input current I * R
8V TO 15V 0.1F VDD 0.1F R20 VIN0_AP VIN0_AM R10 1/2 LTC2970 VIN0_BP RSENSE Q1 TP0610K GND OUT DC/DC CONVERTER FB R10 VIN VEE R20 LOAD VIN0_BM IOUT0 ALERT SCL SDA I2C BUS 12VIN
REF 0.1F
29701 F05
GND ASEL0 ASEL1
Figure 5. Negative Power Supply Application Circuit
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drop across resistor RSENSE. Since the VDD pin voltage is monitored by the LTC2970, its tolerance can be accounted for when calculating the point of load voltage. Transistor Q1 allows the IOUT0 pin to force current into the converter's feedback node without forward biasing the LTC2970's body diode. Note that IOUT0's output current defaults to 128A after the LTC2970 comes out of power-on reset. 15-Bit Programmable Power Supply Application Circuit Figure 6 illustrates how both servo channels of the LTC2970 can be configured to adjust a single DC/DC converter over a 15-bit dynamic range. R30 and R31 are sized to force 1 bit of overlap between the coarse (channel 0) and fine (channel 1) servo loops. One coarse servo iteration should be performed first on channel 0 with IDAC1 programmed to mid-scale, and then channel 1 can be programmed to servo to the desired voltage. Programmable Reference Application Circuit Figure 7 shows a LTC2970 configured as a programmable reference that can span a 0V to 3.5V range with a resolution of 100V and an absolute accuracy of less than 0.5%. The two IDAC's are paralleled by terminating IDAC1's output resistor in the VOUT0 output and taking the output of the composite DAC from VOUT1. IDAC0 should servo once with IDAC1 set to mid-scale, and then IDAC1 can servo once, continuously, or trigger on drift to the desired target voltage.
8V TO 15V 0.1F 12VIN VIN IN OUT
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+
CLOAD LTC2970 VOUT1
VDD GPIO_CFG
0.1F
DC/DC CONVERTER
R31 R30 R20
VOUT0 VIN0_AP VIN1_AP IOUT1 LOAD R10 R41 R40 VIN0_AM IOUT0
ALERT SCL SDA I2C BUS
RUN/SS FB GND SGND R31 R30 * 128 R41 = R40
GPIO_0 REF
VIN1_AM GND ASEL0 ASEL1 0.1F
29701 F06
Figure 6. Programmable Power Supply Application Circuit
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LTC2970/LTC2970-1 PACKAGE DESCRIPTIO U
UFD Package 24-Lead Plastic QFN (4mm x 5mm)
(Reference LTC DWG # 05-08-1696)
2.65 0.10 (2 SIDES) 4.00 0.10 (2 SIDES) 0.70 0.05 4.50 0.05 3.10 0.05 2.65 0.05 (2 SIDES) PIN 1 TOP MARK (NOTE 6) 0.75 0.05 R = 0.115 TYP 23 24 PIN 1 NOTCH R = 0.30 TYP 0.40 0.05 1 2 5.00 0.10 (2 SIDES) 3.65 0.10 (2 SIDES)
(UFD24) QFN 0505
0.25 0.05 0.50 BSC 3.65 0.05 (2 SIDES) 4.10 0.05 5.50 0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
PACKAGE OUTLINE
0.200 REF 0.00 - 0.05
0.25 0.05 0.50 BSC BOTTOM VIEW--EXPOSED PAD
NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X). 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
TYPICAL APPLICATIO
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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8V TO 15V 0.1F 12VIN VDD LTC2970 VIN1_AP VIN1_AM VIN0_AP VIN0_AM VOUT1 22F + VOUT - 100 10 12.7k VOUT0 IOUT0 REF 0.1F
29701 F07
0.1F
ALERT SCL SDA I2C BUS
IOUT1
GND ASEL0 ASEL1
Figure 7. Programmable Reference Application Circuit
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LTC2970/LTC2970-1 TYPICAL APPLICATIO U
8V TO 15V 10 R50 VIN IN OUT 12VIN VDD GPIO_CFG VIN0_BM VIN0_BP VOUT0 VIN0_AP IOUT0 VIN0_AM ALERT SCL 16 GPIO_0 SDA 9 10k I+ I- DC/DC CONVERTER 0 4 3 11 R30 R20 RUN/SS FB R10 PGND SGND LOAD 14 R40 2 17 18 19 I2C BUS SMBUS COMPATIBLE 1 20 0.1F 0.1F
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)
LTC2970 R51 VIN IN OUT
I+ I- DC/DC CONVERTER 1 R31 R21 RUN/SS FB R11 PGND SGND LOAD
8 7 12 5 13 R41 6 15
VIN1_BM VIN1_BP VOUT1 VIN1_AP IOUT1 VIN1_AM REF 23 0.1F GPIO_1 RGND 24
GND ASEL0 ASEL1 25 22 21
29701 TA01
Figure 8. Typical LTC2970 Application Circuit for DC/DC Converters with External Feedback Resistors
RELATED PARTS
PART NUMBER LTC2920-1/LTC2920-2 LTC2921/LTC2922 LTC2923 LTC2924 LTC2925 LTC2926 LTC2927 DESCRIPTION Single/Dual Power Supply Margining Controllers Power Supply Trackers with Input Monitors Power Supply Tracking Controller Quad Power Supply Sequencer Multiple Power Supply Tracking Controller MOSFET Controller Power Supply Tracker Single Power Supply Tracker COMMENTS Symmetric/Asymmetric High and Low Voltage Margining 3 (LTC2921) or 5 (LTC2922) Remote Sense Switches Up to 3 Supplies Voltage Monitoring and Sequence Error Detection and Reporting Power Good Timer, Remote Sense Switch Up to 3 Modules Point of Load Applications
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36 Linear Technology Corporation
(408) 432-1900 FAX: (408) 434-0507
LT 0106 * PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2006

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